ja tam czytam, ze zdania sa b.rozne.
Tutaj np. gosc twierdzi, ze CS8416 wcale nie jest zly ->
http://www.diyaudio.com/forums/showthread/t-47943.htmlQuote:
To me a lot of that FIFO related jitter reduction is only marketing stuff because it\'s such a decriptive explanation.
Feeding that crappy CS8416 with an also crappy low cost spdif source does not show enough phase noise that the sampling data and clocks can\'t be reclocked with a simple D-FF.
Answer:
You\'re half right... the jitter which comes out of a CS8416 is extremely low - It\'s nowhere near the half-of-UI phase noise that would theoretically break D-flip-flop reclocking. Using an oscilloscope (not a phase noise measurement instrument but a good "will this system even work?" instrument) the 8416\'s RMCK output is indistinguishable from a good oscillator.
But this only works if the reclocking clock is frequency and phase locked to the data being reclocked. Since this is coming from a VCXO+PLL with as low a bandwidth as possible, a fast enough drift (warmup?) occuring in either the VCXO or the original source could push the reclocking clock\'s phase off enough to break your reclocker. The lower your VCXO+PLL bandwidth is, the worse this becomes.
Adding a FIFO lets you tolerate much more frequency drift, which lets you push the PLL bandwidth lower offering better jitter rejection.
Marketing? nah, it makes sense.
Doszukalem sie, ze DIR9001 ma jitter: 50 ps.
CS8420 np. ma ponoc 200 ps.
